1. Field of the Invention
The present invention relates generally to the field of semiconductor fabrication and, more particularly, to a method of fabricating high-voltage metal-oxide-semiconductor (MOS) devices.
2. Description of the Prior Art
Integrated circuits (ICs) containing both high-voltage and low-voltage devices such as high/low voltage MOS transistor devices are known in the art. For example, the low-voltage device may be used in the control circuits as the high-voltage device may be used in electrically programmable read only memory (EPROM) or the driving circuits of the liquid crystal display devices.
Please refer to FIG. 1 to FIG. 7. FIGS. 1 to 7 are schematic, cross-sectional diagrams illustrating a method of fabricating a high-voltage NMOS device in accordance with the prior art. As shown in FIG. 1, a semiconductor substrate 10 is provided. The high-voltage NMOS device is formed within the high-voltage P well (HVPW) 12. Shallow trench isolation (STI) structures 14 and 16 are formed in the semiconductor substrate 10. The STI structure 14 defines a high-voltage device area 102, which is further divided into two sub-areas 104 and 106 by STI structure 16.
As shown in FIG. 2, an ion implantation process is carried out to form an N grade diffusion region 20 within the HVPW 12. Subsequently, a pad oxide layer 22 and a pad nitride layer 24 are formed on the surface of the semiconductor substrate 10.
As shown in FIG. 3, the entire high-voltage device area 102 is exposed by selectively etching away the pad oxide layer 22 and the pad nitride layer 24 within the high-voltage device area 102. As shown in FIG. 4, a thick oxide layer 42 (about 850 angstroms for 32V or 42V device) is grown on the exposed semiconductor substrate 10 including sub-areas 104 and 106.
As shown in FIG. 5, a polysilicon gate 52 is patterned on the thick oxide layer 42 of the sub-area 104. The polysilicon gate 52 laterally extends to the STI structure 16.
According to the prior art, a photo-mask is then employed to define a photoresist layer (not shown) over the semiconductor substrate 10. The photoresist layer is used to protect the semiconductor substrate 10 except the high-voltage device area 102. Using the photoresist layer and the polysilicon gate as a hard mask, a dry etching process is performed to etch the thick oxide layer 42.
As shown in FIG. 6, when removing the thick oxide layer 42 within the high-voltage device area 102, which is not covered by the polysilicon gate 52, recessed areas 64 and 66 with hundreds of angstroms are simultaneously formed in the STI structures 14 and 16, respectively.
As shown in FIG. 7, an N+ doping process is carried out to form, within the sub-area 104, an N+ region 72 next to the polysilicon gate 52, and to form, within the sub-area 106, an N+ region 74. The aforementioned recessed areas 64 and 66 adversely affect the doping profile of the N+ regions 72 and 74 as well as the performance of the high-voltage device. As specifically indicated in FIG. 7, through the recessed areas 64 and 66, the N+ doping process also creates downwardly extended tails 72a and 74a. As a result, the N+ region 74 is close to the junction 78 between the HVPW 12 and the N grade diffusion region 20, and the breakdown voltage of the high-voltage device is therefore decreased.
In light of the above, there is a need in this industry to provide an improved method for fabricating high-voltage MOS devices.